In the field of power electronics, a load switch is commonly employed to couple a power supply to a load. The load switch functions to connect and disconnect the power supply and the load. When properly designed, the load switch can also protect both the power supply and the load against faulty conditions. The following are example functions of a load switch:                External enable-signal controlled power switch between power supply and load        Under-voltage lock-out        Slew-rate control to adjust rising rate of load voltage with reduced inrush load current to avoid faulty conditions like CMOS device latch-up. This is also called soft-start in the art        Load current-limiting to avoid hardware damage upon short circuit        Thermal shutdown of load power to avoid hardware overheat        
FIG. 1A illustrates a prior art current limiting load switch (CLLS) 1 for coupling an external power supply Vss 6 to an external load 8. In this case, the external load 8 is a parallel connection of a resistive Rload and a capacitive Cload. Thus, the prior art CLLS 1 delivers a load current Iload to the external load 8 while maintaining a load voltage Vload across it. A power field effect transistor (FET) M1 2 with a low on-resistance Rdson, in this case a P-channel metal-oxide-semiconductor (PMOS) FET, functions as a pass transistor to connect and disconnect the external power supply Vss 6 to the external load 8. Thus, when it is desirable to disconnect the external load 8 from the external power supply Vss 6 the power FET M1 2 will be fully turned OFF.
The prior art CLLS 1 limits the load current Iload to a pre-settable maximum Imax with a feedback loop 12 having a preset fixed reference voltage VR. The fixed reference voltage VR is generated with a pre-settable current mirror 16. During normal operation, the power FET M1 2 is fully turned on and passes the load current Iload from the external power supply Vss 6 to the external load 8. Meanwhile, a sense current Is, that is a portion of the load current Iload, flows through a sense FET M2 4 and a sense resistor Rsense thus developing a sense voltage Vs across the sense resistor Rsense. The feedback loop 12 has a current limiting amplifier 10 with its output 10c driving the common power gate 3b of power FET M1 2 and sense FET M2 4 thus controlling their respective on-resistances. The first input 10a and the second input 10b of the current limiting amplifier 10 are respectively connected to the fixed reference voltage VR and the sense voltage Vs. Under normal operation where the sense current Is is small, the corresponding sense voltage Vs is smaller than the fixed reference voltage VR thus leaving the feedback loop 12 open (the current limiting amplifier output 10c goes into a high-impedance state). However, upon shorting of the external load 8, the load current Iload together with the sense current Is increase drastically causing a corresponding increase of the sense voltage Vs. Upon the sense voltage Vs reaching the fixed reference voltage VR, the feedback loop 12 gets closed via the current limiting amplifier 10 and continuously controls the common power gate 3b of power FET M1 2 and sense FET M2 4 so as to hold the sense voltage Vs equal to the fixed reference voltage VR with the corresponding load current Iload limited to the pre-settable maximum Imax. As another feature of the prior art CLLS 1, it includes a soft-start control circuit 18, having its output in parallel connection with the current limiting amplifier 10 output, for controlling the common power gate 3b of power FET M1 2 and sense FET M2 4 and effecting a controlled slew-rate of the load voltage Vload during power-up. After soft-start, the common power gate 3b is pulled low such that the power FET M1 2 is fully turned on and operates in linear region with a low on-resistance Rdson. To those skilled in the art, as the current limiting amplifier output 10c remains in a high-impedance state during soft-start of the switching circuit, there is no functional interference between the soft-start control circuit 18 and the feedback loop 12. To avoid excessive obscuring details, the internal circuitry of the soft-start control circuit 18 is not illustrated here.
Turning now to a more detailed subsystem level description of the prior art CLLS 1. Power FET M1 2 is the main pass transistor with a low on-resistance Rdson that connects and disconnects the external power supply Vss 6 to the external load 8. Power FET source 2a (S1) is connected to external power supply Vss 6 and common power drain 3c (D) is connected to load voltage Vload of the external load 8. Sense FET M2 4, in this case also a PMOS FET, is a current sensing transistor and it can be made as a small portion of the same semiconductor die as power FET M1 2 with the following being a typical example of selected FET channel width-to-channel length ratio (W/L):RATIOI=Is/Ipower=0.001  (A)                where RATIOI≈W/L(sense FET M2 4)/W/L(power FET M1 2)Equation (A) gives the value of RATIOI when the voltages across the sense FET M2 4 and power FET M1 2 are equal. However, if the voltages across the FETs are not equal, RATIOI may change, as will be shown later. The on resistance ratio, RATIOR of the FETs is fixed whether the FETs are operating in saturation region or linear region:RATIOR=Ron(power FET M1 2)/Ron(sense FET M2 4)=constantIn accordance with equation (A), RATIOR can be set to 0.001.For the purpose of current sensing while maintaining power efficiency, the following criterion is generally followed:RATIOI<<1In which case, Ipower≈Iload. Thus, more generally RATIOI can be selected within the following range:        
RATIOI ranges from about 0.0001 to about 0.1
In essence, power FET M1 2 and sense FET M2 4 are interconnected in a split-source configuration with common power gate 3b and common power drain 3c but a separate sense FET source 4a. In view of equation (A), the load current Iload can therefore be indirectly sensed via sense current Is as it develops a sense voltage Vs across the sense resistor Rsense connected between the sense FET source 4a and the external power supply Vss 6.
As part of the feedback loop 12, the sense voltage Vs is fed to the second input 10b terminal of the current limiting amplifier 10. As another part of the feedback loop 12, the preset fixed reference voltage VR is generated with a VR-generator 14 and is fed to the first input 10a terminal of the current limiting amplifier 10. Within the VR-generator 14, the fixed reference voltage VR is developed across a voltage reference resistor Rref connected between the external power supply Vss 6 and a current output node of the pre-settable current mirror 16 with output current=16. The output current 16 is drain current of an FET M6 that is part of a current mirror pair (FET M5 and FET M6) wherein the FET M5 is loaded with a current source 16a providing a constant current:I4=Isetwhere “Iset” is a pre-settable current level set with an external current setting resistor Rset. Finally, the Iset would, through current mirroring into the output current I6(I6=I4=Iset) then developing the fixed reference voltage VR, cause the feedback loop 12 to limit the load current Iload to the pre-settable maximum Imax upon Vs>VR, which can occur during shorting of the external load 8.
FIG. 1B is an example plot of sense current Is and power current Ipower plus a number of other internal signals of the prior art CLLS 1 versus the load resistance Rload. Additionally, the output impedance (Ro2) of sense FET M2 4 is also plotted. In view of equation (A), Ipower is essentially equal to the load current Iload and thus represents Iload. In this example:
Imax=2.8 Amp (ampere)
VR=43 mV (milliVolt)
It can be seen that while Rload is large (>about 4.2 Ohm) Iload stays below Imax (Region A right side). Here the power FET M1 2 is approximately fully turned on with its common power gate 3b pulled all the way to a low level. As Rload gets continuously reduced, Iload keeps rising. While Iload eventually gets reduced and limited to Imax by the feedback loop 12 for Rload<about 2.7 Ohm (Region B), an anomaly zone of 2.7 Ohm<Rload<4.2 Ohm nevertheless exists wherein an unacceptably high transitional Iload overshoot 50 beyond Imax takes place (Region A left side). In this case, the transitional Iload overshoot 50 reaches as much as 4.4 Amp beyond Imax (2.8 Amp) before the feedback loop 12 closes and limits the current to Imax (Region B). It is therefore important to identify the cause of this transitional Iload overshoot 50 then mitigate it with proper modification of the prior art CLLS 1.